
//      
//      Copyright (c) 2002 Verisilicon  All Rights Reserved.
//     
//      Verilog model for Synchronous Dual-Port SRAM
//      Version:         2.6
//      Verified With:   Cadence Verilog-XL
//
//      Instance Name:   RADP4096X48M16
//      Word Depth:      4096 
//      Word Width:      48 
//      Generation Date: 2011-4-27 5:31:50
//

`timescale 1 ns/10 ps
`celldefine

module RADP4096X48M16 (DAOUT,DBOUT,ADA,ADB,CENA,CENB,CLKA,CLKB,
                      DAIN,DBIN,OEA,OEB,WEA,WEB);
 
  parameter     Word_Width=48;
  parameter     Word_Depth=4096;
  parameter	Addr_Depth=12;
  parameter     We_Number =12;
  parameter     Pt_Number =4;   

  output [Word_Width-1:0] DAOUT;
  output [Word_Width-1:0] DBOUT;
  input                   CLKA;
  input                   CLKB;
  input                   CENA;
  input                   CENB;
  input                   OEA;
  input                   OEB;
  input  [We_Number-1:0]  WEA;
  input  [We_Number-1:0]  WEB;
  input  [Addr_Depth-1:0] ADA;
  input  [Addr_Depth-1:0] ADB;
  input  [Word_Width-1:0] DAIN;
  input  [Word_Width-1:0] DBIN;  
  wire   [Word_Width-1:0] DAOUT_int;
  wire   [Word_Width-1:0] DBOUT_int;
  wire   [Addr_Depth-1:0] ADA_int;
  wire   [Addr_Depth-1:0] ADB_int;
  wire                    CENA_int;
  wire                    CENB_int;
  wire                    CLKA_int;
  wire                    CLKB_int;
  wire   [Word_Width-1:0] DAIN_int;
  wire   [Word_Width-1:0] DBIN_int;  
  wire                    OEA_int;
  wire                    OEB_int;  
  wire   [We_Number-1:0]  WEA_int;
  wire   [We_Number-1:0]  WEB_int;
  reg    [Word_Width-1:0] DAOUT_state;
  reg    [Word_Width-1:0] DBOUT_state;
  reg    [Addr_Depth-1:0] ADA_state;
  reg    [Addr_Depth-1:0] ADB_state;
  reg                     CENA_state;
  reg                     CENB_state;
  reg                     CLKA_state;
  reg                     CLKB_state;  
  reg    [Word_Width-1:0] DAIN_state;
  reg    [Word_Width-1:0] DBIN_state;
  reg    [We_Number-1:0]  WEA_state;
  reg    [We_Number-1:0]  WEB_state;
  reg                     flag_ADA0;
  reg                     flag_ADB0;
  reg                     flag_ADA1;
  reg                     flag_ADB1;
  reg                     flag_ADA2;
  reg                     flag_ADB2;
  reg                     flag_ADA3;
  reg                     flag_ADB3;
  reg                     flag_ADA4;
  reg                     flag_ADB4;
  reg                     flag_ADA5;
  reg                     flag_ADB5;
  reg                     flag_ADA6;
  reg                     flag_ADB6;
  reg                     flag_ADA7;
  reg                     flag_ADB7;
  reg                     flag_ADA8;
  reg                     flag_ADB8;
  reg                     flag_ADA9;
  reg                     flag_ADB9;
  reg                     flag_ADA10;
  reg                     flag_ADB10;
  reg                     flag_ADA11;
  reg                     flag_ADB11;
  reg                     flag_CENA;
  reg                     flag_CENB;
  reg                     flag_CLKA_CYC;
  reg                     flag_CLKA_HT;
  reg                     flag_CLKA_LT;
  reg                     flag_CLKB_CYC;
  reg                     flag_CLKB_HT;
  reg                     flag_CLKB_LT;  
  reg                     flag_DAIN0;
  reg                     flag_DBIN0;
  reg                     flag_DAIN1;
  reg                     flag_DBIN1;
  reg                     flag_DAIN2;
  reg                     flag_DBIN2;
  reg                     flag_DAIN3;
  reg                     flag_DBIN3;
  reg                     flag_DAIN4;
  reg                     flag_DBIN4;
  reg                     flag_DAIN5;
  reg                     flag_DBIN5;
  reg                     flag_DAIN6;
  reg                     flag_DBIN6;
  reg                     flag_DAIN7;
  reg                     flag_DBIN7;
  reg                     flag_DAIN8;
  reg                     flag_DBIN8;
  reg                     flag_DAIN9;
  reg                     flag_DBIN9;
  reg                     flag_DAIN10;
  reg                     flag_DBIN10;
  reg                     flag_DAIN11;
  reg                     flag_DBIN11;
  reg                     flag_DAIN12;
  reg                     flag_DBIN12;
  reg                     flag_DAIN13;
  reg                     flag_DBIN13;
  reg                     flag_DAIN14;
  reg                     flag_DBIN14;
  reg                     flag_DAIN15;
  reg                     flag_DBIN15;
  reg                     flag_DAIN16;
  reg                     flag_DBIN16;
  reg                     flag_DAIN17;
  reg                     flag_DBIN17;
  reg                     flag_DAIN18;
  reg                     flag_DBIN18;
  reg                     flag_DAIN19;
  reg                     flag_DBIN19;
  reg                     flag_DAIN20;
  reg                     flag_DBIN20;
  reg                     flag_DAIN21;
  reg                     flag_DBIN21;
  reg                     flag_DAIN22;
  reg                     flag_DBIN22;
  reg                     flag_DAIN23;
  reg                     flag_DBIN23;
  reg                     flag_DAIN24;
  reg                     flag_DBIN24;
  reg                     flag_DAIN25;
  reg                     flag_DBIN25;
  reg                     flag_DAIN26;
  reg                     flag_DBIN26;
  reg                     flag_DAIN27;
  reg                     flag_DBIN27;
  reg                     flag_DAIN28;
  reg                     flag_DBIN28;
  reg                     flag_DAIN29;
  reg                     flag_DBIN29;
  reg                     flag_DAIN30;
  reg                     flag_DBIN30;
  reg                     flag_DAIN31;
  reg                     flag_DBIN31;
  reg                     flag_DAIN32;
  reg                     flag_DBIN32;
  reg                     flag_DAIN33;
  reg                     flag_DBIN33;
  reg                     flag_DAIN34;
  reg                     flag_DBIN34;
  reg                     flag_DAIN35;
  reg                     flag_DBIN35;
  reg                     flag_DAIN36;
  reg                     flag_DBIN36;
  reg                     flag_DAIN37;
  reg                     flag_DBIN37;
  reg                     flag_DAIN38;
  reg                     flag_DBIN38;
  reg                     flag_DAIN39;
  reg                     flag_DBIN39;
  reg                     flag_DAIN40;
  reg                     flag_DBIN40;
  reg                     flag_DAIN41;
  reg                     flag_DBIN41;
  reg                     flag_DAIN42;
  reg                     flag_DBIN42;
  reg                     flag_DAIN43;
  reg                     flag_DBIN43;
  reg                     flag_DAIN44;
  reg                     flag_DBIN44;
  reg                     flag_DAIN45;
  reg                     flag_DBIN45;
  reg                     flag_DAIN46;
  reg                     flag_DBIN46;
  reg                     flag_DAIN47;
  reg                     flag_DBIN47;
  reg                     flag_VIOA;
  reg                     flag_VIOB;
  reg                     flag_WEA0;
  reg                     flag_WEB0;
  reg                     flag_WEA1;
  reg                     flag_WEB1;
  reg                     flag_WEA2;
  reg                     flag_WEB2;
  reg                     flag_WEA3;
  reg                     flag_WEB3;
  reg                     flag_WEA4;
  reg                     flag_WEB4;
  reg                     flag_WEA5;
  reg                     flag_WEB5;
  reg                     flag_WEA6;
  reg                     flag_WEB6;
  reg                     flag_WEA7;
  reg                     flag_WEB7;
  reg                     flag_WEA8;
  reg                     flag_WEB8;
  reg                     flag_WEA9;
  reg                     flag_WEB9;
  reg                     flag_WEA10;
  reg                     flag_WEB10;
  reg                     flag_WEA11;
  reg                     flag_WEB11;
  reg                     prev_flag_ADA0;
  reg                     prev_flag_ADB0;
  reg                     prev_flag_ADA1;
  reg                     prev_flag_ADB1;
  reg                     prev_flag_ADA2;
  reg                     prev_flag_ADB2;
  reg                     prev_flag_ADA3;
  reg                     prev_flag_ADB3;
  reg                     prev_flag_ADA4;
  reg                     prev_flag_ADB4;
  reg                     prev_flag_ADA5;
  reg                     prev_flag_ADB5;
  reg                     prev_flag_ADA6;
  reg                     prev_flag_ADB6;
  reg                     prev_flag_ADA7;
  reg                     prev_flag_ADB7;
  reg                     prev_flag_ADA8;
  reg                     prev_flag_ADB8;
  reg                     prev_flag_ADA9;
  reg                     prev_flag_ADB9;
  reg                     prev_flag_ADA10;
  reg                     prev_flag_ADB10;
  reg                     prev_flag_ADA11;
  reg                     prev_flag_ADB11;
  reg                     prev_flag_CENA;
  reg                     prev_flag_CENB;
  reg                     prev_flag_CLKA_CYC;
  reg                     prev_flag_CLKA_HT;
  reg                     prev_flag_CLKA_LT;
  reg                     prev_flag_CLKB_CYC;
  reg                     prev_flag_CLKB_HT;
  reg                     prev_flag_CLKB_LT;  
  reg                     prev_flag_DAIN0;
  reg                     prev_flag_DBIN0;
  reg                     prev_flag_DAIN1;
  reg                     prev_flag_DBIN1;
  reg                     prev_flag_DAIN2;
  reg                     prev_flag_DBIN2;
  reg                     prev_flag_DAIN3;
  reg                     prev_flag_DBIN3;
  reg                     prev_flag_DAIN4;
  reg                     prev_flag_DBIN4;
  reg                     prev_flag_DAIN5;
  reg                     prev_flag_DBIN5;
  reg                     prev_flag_DAIN6;
  reg                     prev_flag_DBIN6;
  reg                     prev_flag_DAIN7;
  reg                     prev_flag_DBIN7;
  reg                     prev_flag_DAIN8;
  reg                     prev_flag_DBIN8;
  reg                     prev_flag_DAIN9;
  reg                     prev_flag_DBIN9;
  reg                     prev_flag_DAIN10;
  reg                     prev_flag_DBIN10;
  reg                     prev_flag_DAIN11;
  reg                     prev_flag_DBIN11;
  reg                     prev_flag_DAIN12;
  reg                     prev_flag_DBIN12;
  reg                     prev_flag_DAIN13;
  reg                     prev_flag_DBIN13;
  reg                     prev_flag_DAIN14;
  reg                     prev_flag_DBIN14;
  reg                     prev_flag_DAIN15;
  reg                     prev_flag_DBIN15;
  reg                     prev_flag_DAIN16;
  reg                     prev_flag_DBIN16;
  reg                     prev_flag_DAIN17;
  reg                     prev_flag_DBIN17;
  reg                     prev_flag_DAIN18;
  reg                     prev_flag_DBIN18;
  reg                     prev_flag_DAIN19;
  reg                     prev_flag_DBIN19;
  reg                     prev_flag_DAIN20;
  reg                     prev_flag_DBIN20;
  reg                     prev_flag_DAIN21;
  reg                     prev_flag_DBIN21;
  reg                     prev_flag_DAIN22;
  reg                     prev_flag_DBIN22;
  reg                     prev_flag_DAIN23;
  reg                     prev_flag_DBIN23;
  reg                     prev_flag_DAIN24;
  reg                     prev_flag_DBIN24;
  reg                     prev_flag_DAIN25;
  reg                     prev_flag_DBIN25;
  reg                     prev_flag_DAIN26;
  reg                     prev_flag_DBIN26;
  reg                     prev_flag_DAIN27;
  reg                     prev_flag_DBIN27;
  reg                     prev_flag_DAIN28;
  reg                     prev_flag_DBIN28;
  reg                     prev_flag_DAIN29;
  reg                     prev_flag_DBIN29;
  reg                     prev_flag_DAIN30;
  reg                     prev_flag_DBIN30;
  reg                     prev_flag_DAIN31;
  reg                     prev_flag_DBIN31;
  reg                     prev_flag_DAIN32;
  reg                     prev_flag_DBIN32;
  reg                     prev_flag_DAIN33;
  reg                     prev_flag_DBIN33;
  reg                     prev_flag_DAIN34;
  reg                     prev_flag_DBIN34;
  reg                     prev_flag_DAIN35;
  reg                     prev_flag_DBIN35;
  reg                     prev_flag_DAIN36;
  reg                     prev_flag_DBIN36;
  reg                     prev_flag_DAIN37;
  reg                     prev_flag_DBIN37;
  reg                     prev_flag_DAIN38;
  reg                     prev_flag_DBIN38;
  reg                     prev_flag_DAIN39;
  reg                     prev_flag_DBIN39;
  reg                     prev_flag_DAIN40;
  reg                     prev_flag_DBIN40;
  reg                     prev_flag_DAIN41;
  reg                     prev_flag_DBIN41;
  reg                     prev_flag_DAIN42;
  reg                     prev_flag_DBIN42;
  reg                     prev_flag_DAIN43;
  reg                     prev_flag_DBIN43;
  reg                     prev_flag_DAIN44;
  reg                     prev_flag_DBIN44;
  reg                     prev_flag_DAIN45;
  reg                     prev_flag_DBIN45;
  reg                     prev_flag_DAIN46;
  reg                     prev_flag_DBIN46;
  reg                     prev_flag_DAIN47;
  reg                     prev_flag_DBIN47;
  reg                     prev_flag_VIOA;
  reg                     prev_flag_VIOB;
  reg                     prev_flag_WEA0;
  reg                     prev_flag_WEB0; 
  reg                     prev_flag_WEA1;
  reg                     prev_flag_WEB1; 
  reg                     prev_flag_WEA2;
  reg                     prev_flag_WEB2; 
  reg                     prev_flag_WEA3;
  reg                     prev_flag_WEB3; 
  reg                     prev_flag_WEA4;
  reg                     prev_flag_WEB4; 
  reg                     prev_flag_WEA5;
  reg                     prev_flag_WEB5; 
  reg                     prev_flag_WEA6;
  reg                     prev_flag_WEB6; 
  reg                     prev_flag_WEA7;
  reg                     prev_flag_WEB7; 
  reg                     prev_flag_WEA8;
  reg                     prev_flag_WEB8; 
  reg                     prev_flag_WEA9;
  reg                     prev_flag_WEB9; 
  reg                     prev_flag_WEA10;
  reg                     prev_flag_WEB10; 
  reg                     prev_flag_WEA11;
  reg                     prev_flag_WEB11; 
  reg                     prev_CLKA;
  reg                     prev_CLKB;
  wire                    flag_opA;
  wire                    flag_opB;
  wire                    flag_wrA0;  
  wire                    flag_wrB0;
  wire                    flag_wrA1;  
  wire                    flag_wrB1;
  wire                    flag_wrA2;  
  wire                    flag_wrB2;
  wire                    flag_wrA3;  
  wire                    flag_wrB3;
  wire                    flag_wrA4;  
  wire                    flag_wrB4;
  wire                    flag_wrA5;  
  wire                    flag_wrB5;
  wire                    flag_wrA6;  
  wire                    flag_wrB6;
  wire                    flag_wrA7;  
  wire                    flag_wrB7;
  wire                    flag_wrA8;  
  wire                    flag_wrB8;
  wire                    flag_wrA9;  
  wire                    flag_wrB9;
  wire                    flag_wrA10;  
  wire                    flag_wrB10;
  wire                    flag_wrA11;  
  wire                    flag_wrB11;
  wire                    flag_confA;
  wire                    flag_confB;
  wire                    flag_conf;
  reg    [Word_Width-1:0] mem_array[Word_Depth-1:0]; 
  reg    [Word_Width-1:0] t_data;
  integer                 i,j,wn,lbit,hbit;
  
  bufif1 daout_buf[Word_Width-1:0] (DAOUT,DAOUT_int,OEA_int);
  bufif1 dbout_buf[Word_Width-1:0] (DBOUT,DBOUT_int,OEB_int);
  buf ada_buf[Addr_Depth-1:0] (ADA_int,ADA);
  buf adb_buf[Addr_Depth-1:0] (ADB_int,ADB);
  buf (CENA_int,CENA);
  buf (CENB_int,CENB);
  buf (CLKA_int,CLKA);
  buf (CLKB_int,CLKB);
  buf dain_buf[Word_Width-1:0] (DAIN_int,DAIN);
  buf dbin_buf[Word_Width-1:0] (DBIN_int,DBIN);
  buf (OEA_int,OEA);
  buf (OEB_int,OEB);  
  buf wea_buf[We_Number-1:0] (WEA_int,WEA);
  buf web_buf[We_Number-1:0] (WEB_int,WEB);

  assign DAOUT_int=DAOUT_state;
  assign DBOUT_int=DBOUT_state;
  assign flag_confA=(ADA_int===ADB_state) && ((|WEA_int!==1'b0) || (|WEB_state!== 1'b0)) 
                    && (CENA_int!==1'b1) && (CENB_state!==1'b1);
  assign flag_confB=(ADB_int===ADA_state) && ((|WEB_int!==1'b0) || (|WEA_state!== 1'b0)) 
                    && (CENB_int!==1'b1) && (CENA_state!==1'b1);		         
  assign flag_conf =(ADB_int===ADA_int) && ((|WEB_int!== 1'b0) || (|WEA_int!==1'b0)) 
                    && (CENB_int!==1'b1) && (CENA_int!==1'b1);
  assign flag_opA=!CENA_int;
  assign flag_opB=!CENB_int;
  assign flag_wrA0=(!CENA_int && WEA_int[0]);
  assign flag_wrB0=(!CENB_int && WEB_int[0]);
  assign flag_wrA1=(!CENA_int && WEA_int[1]);
  assign flag_wrB1=(!CENB_int && WEB_int[1]);
  assign flag_wrA2=(!CENA_int && WEA_int[2]);
  assign flag_wrB2=(!CENB_int && WEB_int[2]);
  assign flag_wrA3=(!CENA_int && WEA_int[3]);
  assign flag_wrB3=(!CENB_int && WEB_int[3]);
  assign flag_wrA4=(!CENA_int && WEA_int[4]);
  assign flag_wrB4=(!CENB_int && WEB_int[4]);
  assign flag_wrA5=(!CENA_int && WEA_int[5]);
  assign flag_wrB5=(!CENB_int && WEB_int[5]);
  assign flag_wrA6=(!CENA_int && WEA_int[6]);
  assign flag_wrB6=(!CENB_int && WEB_int[6]);
  assign flag_wrA7=(!CENA_int && WEA_int[7]);
  assign flag_wrB7=(!CENB_int && WEB_int[7]);
  assign flag_wrA8=(!CENA_int && WEA_int[8]);
  assign flag_wrB8=(!CENB_int && WEB_int[8]);
  assign flag_wrA9=(!CENA_int && WEA_int[9]);
  assign flag_wrB9=(!CENB_int && WEB_int[9]);
  assign flag_wrA10=(!CENA_int && WEA_int[10]);
  assign flag_wrB10=(!CENB_int && WEB_int[10]);
  assign flag_wrA11=(!CENA_int && WEA_int[11]);
  assign flag_wrB11=(!CENB_int && WEB_int[11]);
  
  always @(CLKA_int)
    begin
      CLKA_state=1'b0;
      if(CLKA_int===1'b1 && prev_CLKA===1'b0)
	begin
	  ADA_state=ADA_int;
	  DAIN_state=DAIN_int;
	  WEA_state=WEA_int;
	  CENA_state=CENA_int;
	  rw_memA;
	end
      else if(CLKA_int===1'bx) 
        begin
	  CLKA_state=1'bx;
	  rw_memA;
	end 
      prev_CLKA=CLKA_int;
    end
    
  always @(CLKB_int)
    begin
      CLKB_state=1'b0;
      if(CLKB_int===1'b1 && prev_CLKB===1'b0)
	begin
	  ADB_state=ADB_int;
	  DBIN_state=DBIN_int;
	  WEB_state=WEB_int;
	  CENB_state=CENB_int;
	  rw_memB;
	end
      else if(CLKB_int===1'bx) 
        begin
	  CLKB_state=1'bx;
	  rw_memB;
	end 
      prev_CLKB=CLKB_int;
    end
    
  always @(flag_CENA
           or flag_ADA0
           or flag_ADA1
           or flag_ADA2
           or flag_ADA3
           or flag_ADA4
           or flag_ADA5
           or flag_ADA6
           or flag_ADA7
           or flag_ADA8
           or flag_ADA9
           or flag_ADA10
           or flag_ADA11
           or flag_CLKA_CYC or flag_CLKA_HT or flag_CLKA_LT
           or flag_DAIN0
           or flag_DAIN1
           or flag_DAIN2
           or flag_DAIN3
           or flag_DAIN4
           or flag_DAIN5
           or flag_DAIN6
           or flag_DAIN7
           or flag_DAIN8
           or flag_DAIN9
           or flag_DAIN10
           or flag_DAIN11
           or flag_DAIN12
           or flag_DAIN13
           or flag_DAIN14
           or flag_DAIN15
           or flag_DAIN16
           or flag_DAIN17
           or flag_DAIN18
           or flag_DAIN19
           or flag_DAIN20
           or flag_DAIN21
           or flag_DAIN22
           or flag_DAIN23
           or flag_DAIN24
           or flag_DAIN25
           or flag_DAIN26
           or flag_DAIN27
           or flag_DAIN28
           or flag_DAIN29
           or flag_DAIN30
           or flag_DAIN31
           or flag_DAIN32
           or flag_DAIN33
           or flag_DAIN34
           or flag_DAIN35
           or flag_DAIN36
           or flag_DAIN37
           or flag_DAIN38
           or flag_DAIN39
           or flag_DAIN40
           or flag_DAIN41
           or flag_DAIN42
           or flag_DAIN43
           or flag_DAIN44
           or flag_DAIN45
           or flag_DAIN46
           or flag_DAIN47
           or flag_VIOA 
           or flag_WEA0
           or flag_WEA1
           or flag_WEA2
           or flag_WEA3
           or flag_WEA4
           or flag_WEA5
           or flag_WEA6
           or flag_WEA7
           or flag_WEA8
           or flag_WEA9
           or flag_WEA10
           or flag_WEA11
          )
    begin
      if(flag_ADA0!==prev_flag_ADA0) 
        ADA_state[0]=1'bx;
      prev_flag_ADA0=flag_ADA0;    
      if(flag_ADA1!==prev_flag_ADA1) 
        ADA_state[1]=1'bx;
      prev_flag_ADA1=flag_ADA1;    
      if(flag_ADA2!==prev_flag_ADA2) 
        ADA_state[2]=1'bx;
      prev_flag_ADA2=flag_ADA2;    
      if(flag_ADA3!==prev_flag_ADA3) 
        ADA_state[3]=1'bx;
      prev_flag_ADA3=flag_ADA3;    
      if(flag_ADA4!==prev_flag_ADA4) 
        ADA_state[4]=1'bx;
      prev_flag_ADA4=flag_ADA4;    
      if(flag_ADA5!==prev_flag_ADA5) 
        ADA_state[5]=1'bx;
      prev_flag_ADA5=flag_ADA5;    
      if(flag_ADA6!==prev_flag_ADA6) 
        ADA_state[6]=1'bx;
      prev_flag_ADA6=flag_ADA6;    
      if(flag_ADA7!==prev_flag_ADA7) 
        ADA_state[7]=1'bx;
      prev_flag_ADA7=flag_ADA7;    
      if(flag_ADA8!==prev_flag_ADA8) 
        ADA_state[8]=1'bx;
      prev_flag_ADA8=flag_ADA8;    
      if(flag_ADA9!==prev_flag_ADA9) 
        ADA_state[9]=1'bx;
      prev_flag_ADA9=flag_ADA9;    
      if(flag_ADA10!==prev_flag_ADA10) 
        ADA_state[10]=1'bx;
      prev_flag_ADA10=flag_ADA10;    
      if(flag_ADA11!==prev_flag_ADA11) 
        ADA_state[11]=1'bx;
      prev_flag_ADA11=flag_ADA11;    
      if(flag_CENA!==prev_flag_CENA) 
        CENA_state=1'bx;
      prev_flag_CENA=flag_CENA;
      if(!(flag_CLKA_CYC===prev_flag_CLKA_CYC) &&
    	 (flag_CLKA_HT===prev_flag_CLKA_HT) &&
    	 (flag_CLKA_LT===prev_flag_CLKA_LT))
  	if(CENA_int!==1'b1) CLKA_state=1'bx;
      prev_flag_CLKA_CYC=flag_CLKA_CYC;
      prev_flag_CLKA_HT=flag_CLKA_HT;
      prev_flag_CLKA_LT=flag_CLKA_LT;
      if(flag_DAIN0!==prev_flag_DAIN0) 
        DAIN_state[0]=1'bx;
      prev_flag_DAIN0=flag_DAIN0;
      if(flag_DAIN1!==prev_flag_DAIN1) 
        DAIN_state[1]=1'bx;
      prev_flag_DAIN1=flag_DAIN1;
      if(flag_DAIN2!==prev_flag_DAIN2) 
        DAIN_state[2]=1'bx;
      prev_flag_DAIN2=flag_DAIN2;
      if(flag_DAIN3!==prev_flag_DAIN3) 
        DAIN_state[3]=1'bx;
      prev_flag_DAIN3=flag_DAIN3;
      if(flag_DAIN4!==prev_flag_DAIN4) 
        DAIN_state[4]=1'bx;
      prev_flag_DAIN4=flag_DAIN4;
      if(flag_DAIN5!==prev_flag_DAIN5) 
        DAIN_state[5]=1'bx;
      prev_flag_DAIN5=flag_DAIN5;
      if(flag_DAIN6!==prev_flag_DAIN6) 
        DAIN_state[6]=1'bx;
      prev_flag_DAIN6=flag_DAIN6;
      if(flag_DAIN7!==prev_flag_DAIN7) 
        DAIN_state[7]=1'bx;
      prev_flag_DAIN7=flag_DAIN7;
      if(flag_DAIN8!==prev_flag_DAIN8) 
        DAIN_state[8]=1'bx;
      prev_flag_DAIN8=flag_DAIN8;
      if(flag_DAIN9!==prev_flag_DAIN9) 
        DAIN_state[9]=1'bx;
      prev_flag_DAIN9=flag_DAIN9;
      if(flag_DAIN10!==prev_flag_DAIN10) 
        DAIN_state[10]=1'bx;
      prev_flag_DAIN10=flag_DAIN10;
      if(flag_DAIN11!==prev_flag_DAIN11) 
        DAIN_state[11]=1'bx;
      prev_flag_DAIN11=flag_DAIN11;
      if(flag_DAIN12!==prev_flag_DAIN12) 
        DAIN_state[12]=1'bx;
      prev_flag_DAIN12=flag_DAIN12;
      if(flag_DAIN13!==prev_flag_DAIN13) 
        DAIN_state[13]=1'bx;
      prev_flag_DAIN13=flag_DAIN13;
      if(flag_DAIN14!==prev_flag_DAIN14) 
        DAIN_state[14]=1'bx;
      prev_flag_DAIN14=flag_DAIN14;
      if(flag_DAIN15!==prev_flag_DAIN15) 
        DAIN_state[15]=1'bx;
      prev_flag_DAIN15=flag_DAIN15;
      if(flag_DAIN16!==prev_flag_DAIN16) 
        DAIN_state[16]=1'bx;
      prev_flag_DAIN16=flag_DAIN16;
      if(flag_DAIN17!==prev_flag_DAIN17) 
        DAIN_state[17]=1'bx;
      prev_flag_DAIN17=flag_DAIN17;
      if(flag_DAIN18!==prev_flag_DAIN18) 
        DAIN_state[18]=1'bx;
      prev_flag_DAIN18=flag_DAIN18;
      if(flag_DAIN19!==prev_flag_DAIN19) 
        DAIN_state[19]=1'bx;
      prev_flag_DAIN19=flag_DAIN19;
      if(flag_DAIN20!==prev_flag_DAIN20) 
        DAIN_state[20]=1'bx;
      prev_flag_DAIN20=flag_DAIN20;
      if(flag_DAIN21!==prev_flag_DAIN21) 
        DAIN_state[21]=1'bx;
      prev_flag_DAIN21=flag_DAIN21;
      if(flag_DAIN22!==prev_flag_DAIN22) 
        DAIN_state[22]=1'bx;
      prev_flag_DAIN22=flag_DAIN22;
      if(flag_DAIN23!==prev_flag_DAIN23) 
        DAIN_state[23]=1'bx;
      prev_flag_DAIN23=flag_DAIN23;
      if(flag_DAIN24!==prev_flag_DAIN24) 
        DAIN_state[24]=1'bx;
      prev_flag_DAIN24=flag_DAIN24;
      if(flag_DAIN25!==prev_flag_DAIN25) 
        DAIN_state[25]=1'bx;
      prev_flag_DAIN25=flag_DAIN25;
      if(flag_DAIN26!==prev_flag_DAIN26) 
        DAIN_state[26]=1'bx;
      prev_flag_DAIN26=flag_DAIN26;
      if(flag_DAIN27!==prev_flag_DAIN27) 
        DAIN_state[27]=1'bx;
      prev_flag_DAIN27=flag_DAIN27;
      if(flag_DAIN28!==prev_flag_DAIN28) 
        DAIN_state[28]=1'bx;
      prev_flag_DAIN28=flag_DAIN28;
      if(flag_DAIN29!==prev_flag_DAIN29) 
        DAIN_state[29]=1'bx;
      prev_flag_DAIN29=flag_DAIN29;
      if(flag_DAIN30!==prev_flag_DAIN30) 
        DAIN_state[30]=1'bx;
      prev_flag_DAIN30=flag_DAIN30;
      if(flag_DAIN31!==prev_flag_DAIN31) 
        DAIN_state[31]=1'bx;
      prev_flag_DAIN31=flag_DAIN31;
      if(flag_DAIN32!==prev_flag_DAIN32) 
        DAIN_state[32]=1'bx;
      prev_flag_DAIN32=flag_DAIN32;
      if(flag_DAIN33!==prev_flag_DAIN33) 
        DAIN_state[33]=1'bx;
      prev_flag_DAIN33=flag_DAIN33;
      if(flag_DAIN34!==prev_flag_DAIN34) 
        DAIN_state[34]=1'bx;
      prev_flag_DAIN34=flag_DAIN34;
      if(flag_DAIN35!==prev_flag_DAIN35) 
        DAIN_state[35]=1'bx;
      prev_flag_DAIN35=flag_DAIN35;
      if(flag_DAIN36!==prev_flag_DAIN36) 
        DAIN_state[36]=1'bx;
      prev_flag_DAIN36=flag_DAIN36;
      if(flag_DAIN37!==prev_flag_DAIN37) 
        DAIN_state[37]=1'bx;
      prev_flag_DAIN37=flag_DAIN37;
      if(flag_DAIN38!==prev_flag_DAIN38) 
        DAIN_state[38]=1'bx;
      prev_flag_DAIN38=flag_DAIN38;
      if(flag_DAIN39!==prev_flag_DAIN39) 
        DAIN_state[39]=1'bx;
      prev_flag_DAIN39=flag_DAIN39;
      if(flag_DAIN40!==prev_flag_DAIN40) 
        DAIN_state[40]=1'bx;
      prev_flag_DAIN40=flag_DAIN40;
      if(flag_DAIN41!==prev_flag_DAIN41) 
        DAIN_state[41]=1'bx;
      prev_flag_DAIN41=flag_DAIN41;
      if(flag_DAIN42!==prev_flag_DAIN42) 
        DAIN_state[42]=1'bx;
      prev_flag_DAIN42=flag_DAIN42;
      if(flag_DAIN43!==prev_flag_DAIN43) 
        DAIN_state[43]=1'bx;
      prev_flag_DAIN43=flag_DAIN43;
      if(flag_DAIN44!==prev_flag_DAIN44) 
        DAIN_state[44]=1'bx;
      prev_flag_DAIN44=flag_DAIN44;
      if(flag_DAIN45!==prev_flag_DAIN45) 
        DAIN_state[45]=1'bx;
      prev_flag_DAIN45=flag_DAIN45;
      if(flag_DAIN46!==prev_flag_DAIN46) 
        DAIN_state[46]=1'bx;
      prev_flag_DAIN46=flag_DAIN46;
      if(flag_DAIN47!==prev_flag_DAIN47) 
        DAIN_state[47]=1'bx;
      prev_flag_DAIN47=flag_DAIN47;
      if(flag_WEA0!==prev_flag_WEA0)
        WEA_state[0]=1'bx;
      prev_flag_WEA0=flag_WEA0;
      if(flag_WEA1!==prev_flag_WEA1)
        WEA_state[1]=1'bx;
      prev_flag_WEA1=flag_WEA1;
      if(flag_WEA2!==prev_flag_WEA2)
        WEA_state[2]=1'bx;
      prev_flag_WEA2=flag_WEA2;
      if(flag_WEA3!==prev_flag_WEA3)
        WEA_state[3]=1'bx;
      prev_flag_WEA3=flag_WEA3;
      if(flag_WEA4!==prev_flag_WEA4)
        WEA_state[4]=1'bx;
      prev_flag_WEA4=flag_WEA4;
      if(flag_WEA5!==prev_flag_WEA5)
        WEA_state[5]=1'bx;
      prev_flag_WEA5=flag_WEA5;
      if(flag_WEA6!==prev_flag_WEA6)
        WEA_state[6]=1'bx;
      prev_flag_WEA6=flag_WEA6;
      if(flag_WEA7!==prev_flag_WEA7)
        WEA_state[7]=1'bx;
      prev_flag_WEA7=flag_WEA7;
      if(flag_WEA8!==prev_flag_WEA8)
        WEA_state[8]=1'bx;
      prev_flag_WEA8=flag_WEA8;
      if(flag_WEA9!==prev_flag_WEA9)
        WEA_state[9]=1'bx;
      prev_flag_WEA9=flag_WEA9;
      if(flag_WEA10!==prev_flag_WEA10)
        WEA_state[10]=1'bx;
      prev_flag_WEA10=flag_WEA10;
      if(flag_WEA11!==prev_flag_WEA11)
        WEA_state[11]=1'bx;
      prev_flag_WEA11=flag_WEA11;
      if(flag_VIOA!==prev_flag_VIOA)
        begin
	  for(wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEB_state[wn]===1'b0 && WEA_int[wn] !==1'b0)
	        for(i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
	      else if(WEA_int[wn]===1'b0 && WEB_state[wn] !==1'b0)
	        for(i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
	      else if(WEA_int[wn] !==1'b0)
   	        begin
                  if(^(ADA_int)===1'bx)
   	            begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
   	            end
		  else
		    begin
		      t_data=mem_array[ADA_int];
   	              for(i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
		       mem_array[ADA_int]=t_data;
   	            end
                end
	    end	    
	  prev_flag_VIOA=flag_VIOA;
	end
      else 
        rw_memA;
    end


  always @(flag_CENB
           or flag_ADB0
           or flag_ADB1
           or flag_ADB2
           or flag_ADB3
           or flag_ADB4
           or flag_ADB5
           or flag_ADB6
           or flag_ADB7
           or flag_ADB8
           or flag_ADB9
           or flag_ADB10
           or flag_ADB11
           or flag_CLKB_CYC or flag_CLKB_HT or flag_CLKB_LT
           or flag_DBIN0
           or flag_DBIN1
           or flag_DBIN2
           or flag_DBIN3
           or flag_DBIN4
           or flag_DBIN5
           or flag_DBIN6
           or flag_DBIN7
           or flag_DBIN8
           or flag_DBIN9
           or flag_DBIN10
           or flag_DBIN11
           or flag_DBIN12
           or flag_DBIN13
           or flag_DBIN14
           or flag_DBIN15
           or flag_DBIN16
           or flag_DBIN17
           or flag_DBIN18
           or flag_DBIN19
           or flag_DBIN20
           or flag_DBIN21
           or flag_DBIN22
           or flag_DBIN23
           or flag_DBIN24
           or flag_DBIN25
           or flag_DBIN26
           or flag_DBIN27
           or flag_DBIN28
           or flag_DBIN29
           or flag_DBIN30
           or flag_DBIN31
           or flag_DBIN32
           or flag_DBIN33
           or flag_DBIN34
           or flag_DBIN35
           or flag_DBIN36
           or flag_DBIN37
           or flag_DBIN38
           or flag_DBIN39
           or flag_DBIN40
           or flag_DBIN41
           or flag_DBIN42
           or flag_DBIN43
           or flag_DBIN44
           or flag_DBIN45
           or flag_DBIN46
           or flag_DBIN47
           or flag_VIOB 
           or flag_WEB0
           or flag_WEB1
           or flag_WEB2
           or flag_WEB3
           or flag_WEB4
           or flag_WEB5
           or flag_WEB6
           or flag_WEB7
           or flag_WEB8
           or flag_WEB9
           or flag_WEB10
           or flag_WEB11
          )
    begin
      if(flag_ADB0!==prev_flag_ADB0) 
        ADB_state[0]=1'bx;
      prev_flag_ADB0=flag_ADB0;    
      if(flag_ADB1!==prev_flag_ADB1) 
        ADB_state[1]=1'bx;
      prev_flag_ADB1=flag_ADB1;    
      if(flag_ADB2!==prev_flag_ADB2) 
        ADB_state[2]=1'bx;
      prev_flag_ADB2=flag_ADB2;    
      if(flag_ADB3!==prev_flag_ADB3) 
        ADB_state[3]=1'bx;
      prev_flag_ADB3=flag_ADB3;    
      if(flag_ADB4!==prev_flag_ADB4) 
        ADB_state[4]=1'bx;
      prev_flag_ADB4=flag_ADB4;    
      if(flag_ADB5!==prev_flag_ADB5) 
        ADB_state[5]=1'bx;
      prev_flag_ADB5=flag_ADB5;    
      if(flag_ADB6!==prev_flag_ADB6) 
        ADB_state[6]=1'bx;
      prev_flag_ADB6=flag_ADB6;    
      if(flag_ADB7!==prev_flag_ADB7) 
        ADB_state[7]=1'bx;
      prev_flag_ADB7=flag_ADB7;    
      if(flag_ADB8!==prev_flag_ADB8) 
        ADB_state[8]=1'bx;
      prev_flag_ADB8=flag_ADB8;    
      if(flag_ADB9!==prev_flag_ADB9) 
        ADB_state[9]=1'bx;
      prev_flag_ADB9=flag_ADB9;    
      if(flag_ADB10!==prev_flag_ADB10) 
        ADB_state[10]=1'bx;
      prev_flag_ADB10=flag_ADB10;    
      if(flag_ADB11!==prev_flag_ADB11) 
        ADB_state[11]=1'bx;
      prev_flag_ADB11=flag_ADB11;    
      if(flag_CENB!==prev_flag_CENB) 
        CENB_state=1'bx;
      prev_flag_CENB=flag_CENB;
      if(!((flag_CLKB_CYC===prev_flag_CLKB_CYC) &&
    	 (flag_CLKB_HT===prev_flag_CLKB_HT) &&
    	 (flag_CLKB_LT===prev_flag_CLKB_LT)))
  	if(CENB_int!==1'b1) CLKB_state=1'bx;
      prev_flag_CLKB_CYC=flag_CLKB_CYC;
      prev_flag_CLKB_HT=flag_CLKB_HT;
      prev_flag_CLKB_LT=flag_CLKB_LT;
      if(flag_DBIN0!==prev_flag_DBIN0) 
        DBIN_state[0]=1'bx;
      prev_flag_DBIN0=flag_DBIN0;
      if(flag_DBIN1!==prev_flag_DBIN1) 
        DBIN_state[1]=1'bx;
      prev_flag_DBIN1=flag_DBIN1;
      if(flag_DBIN2!==prev_flag_DBIN2) 
        DBIN_state[2]=1'bx;
      prev_flag_DBIN2=flag_DBIN2;
      if(flag_DBIN3!==prev_flag_DBIN3) 
        DBIN_state[3]=1'bx;
      prev_flag_DBIN3=flag_DBIN3;
      if(flag_DBIN4!==prev_flag_DBIN4) 
        DBIN_state[4]=1'bx;
      prev_flag_DBIN4=flag_DBIN4;
      if(flag_DBIN5!==prev_flag_DBIN5) 
        DBIN_state[5]=1'bx;
      prev_flag_DBIN5=flag_DBIN5;
      if(flag_DBIN6!==prev_flag_DBIN6) 
        DBIN_state[6]=1'bx;
      prev_flag_DBIN6=flag_DBIN6;
      if(flag_DBIN7!==prev_flag_DBIN7) 
        DBIN_state[7]=1'bx;
      prev_flag_DBIN7=flag_DBIN7;
      if(flag_DBIN8!==prev_flag_DBIN8) 
        DBIN_state[8]=1'bx;
      prev_flag_DBIN8=flag_DBIN8;
      if(flag_DBIN9!==prev_flag_DBIN9) 
        DBIN_state[9]=1'bx;
      prev_flag_DBIN9=flag_DBIN9;
      if(flag_DBIN10!==prev_flag_DBIN10) 
        DBIN_state[10]=1'bx;
      prev_flag_DBIN10=flag_DBIN10;
      if(flag_DBIN11!==prev_flag_DBIN11) 
        DBIN_state[11]=1'bx;
      prev_flag_DBIN11=flag_DBIN11;
      if(flag_DBIN12!==prev_flag_DBIN12) 
        DBIN_state[12]=1'bx;
      prev_flag_DBIN12=flag_DBIN12;
      if(flag_DBIN13!==prev_flag_DBIN13) 
        DBIN_state[13]=1'bx;
      prev_flag_DBIN13=flag_DBIN13;
      if(flag_DBIN14!==prev_flag_DBIN14) 
        DBIN_state[14]=1'bx;
      prev_flag_DBIN14=flag_DBIN14;
      if(flag_DBIN15!==prev_flag_DBIN15) 
        DBIN_state[15]=1'bx;
      prev_flag_DBIN15=flag_DBIN15;
      if(flag_DBIN16!==prev_flag_DBIN16) 
        DBIN_state[16]=1'bx;
      prev_flag_DBIN16=flag_DBIN16;
      if(flag_DBIN17!==prev_flag_DBIN17) 
        DBIN_state[17]=1'bx;
      prev_flag_DBIN17=flag_DBIN17;
      if(flag_DBIN18!==prev_flag_DBIN18) 
        DBIN_state[18]=1'bx;
      prev_flag_DBIN18=flag_DBIN18;
      if(flag_DBIN19!==prev_flag_DBIN19) 
        DBIN_state[19]=1'bx;
      prev_flag_DBIN19=flag_DBIN19;
      if(flag_DBIN20!==prev_flag_DBIN20) 
        DBIN_state[20]=1'bx;
      prev_flag_DBIN20=flag_DBIN20;
      if(flag_DBIN21!==prev_flag_DBIN21) 
        DBIN_state[21]=1'bx;
      prev_flag_DBIN21=flag_DBIN21;
      if(flag_DBIN22!==prev_flag_DBIN22) 
        DBIN_state[22]=1'bx;
      prev_flag_DBIN22=flag_DBIN22;
      if(flag_DBIN23!==prev_flag_DBIN23) 
        DBIN_state[23]=1'bx;
      prev_flag_DBIN23=flag_DBIN23;
      if(flag_DBIN24!==prev_flag_DBIN24) 
        DBIN_state[24]=1'bx;
      prev_flag_DBIN24=flag_DBIN24;
      if(flag_DBIN25!==prev_flag_DBIN25) 
        DBIN_state[25]=1'bx;
      prev_flag_DBIN25=flag_DBIN25;
      if(flag_DBIN26!==prev_flag_DBIN26) 
        DBIN_state[26]=1'bx;
      prev_flag_DBIN26=flag_DBIN26;
      if(flag_DBIN27!==prev_flag_DBIN27) 
        DBIN_state[27]=1'bx;
      prev_flag_DBIN27=flag_DBIN27;
      if(flag_DBIN28!==prev_flag_DBIN28) 
        DBIN_state[28]=1'bx;
      prev_flag_DBIN28=flag_DBIN28;
      if(flag_DBIN29!==prev_flag_DBIN29) 
        DBIN_state[29]=1'bx;
      prev_flag_DBIN29=flag_DBIN29;
      if(flag_DBIN30!==prev_flag_DBIN30) 
        DBIN_state[30]=1'bx;
      prev_flag_DBIN30=flag_DBIN30;
      if(flag_DBIN31!==prev_flag_DBIN31) 
        DBIN_state[31]=1'bx;
      prev_flag_DBIN31=flag_DBIN31;
      if(flag_DBIN32!==prev_flag_DBIN32) 
        DBIN_state[32]=1'bx;
      prev_flag_DBIN32=flag_DBIN32;
      if(flag_DBIN33!==prev_flag_DBIN33) 
        DBIN_state[33]=1'bx;
      prev_flag_DBIN33=flag_DBIN33;
      if(flag_DBIN34!==prev_flag_DBIN34) 
        DBIN_state[34]=1'bx;
      prev_flag_DBIN34=flag_DBIN34;
      if(flag_DBIN35!==prev_flag_DBIN35) 
        DBIN_state[35]=1'bx;
      prev_flag_DBIN35=flag_DBIN35;
      if(flag_DBIN36!==prev_flag_DBIN36) 
        DBIN_state[36]=1'bx;
      prev_flag_DBIN36=flag_DBIN36;
      if(flag_DBIN37!==prev_flag_DBIN37) 
        DBIN_state[37]=1'bx;
      prev_flag_DBIN37=flag_DBIN37;
      if(flag_DBIN38!==prev_flag_DBIN38) 
        DBIN_state[38]=1'bx;
      prev_flag_DBIN38=flag_DBIN38;
      if(flag_DBIN39!==prev_flag_DBIN39) 
        DBIN_state[39]=1'bx;
      prev_flag_DBIN39=flag_DBIN39;
      if(flag_DBIN40!==prev_flag_DBIN40) 
        DBIN_state[40]=1'bx;
      prev_flag_DBIN40=flag_DBIN40;
      if(flag_DBIN41!==prev_flag_DBIN41) 
        DBIN_state[41]=1'bx;
      prev_flag_DBIN41=flag_DBIN41;
      if(flag_DBIN42!==prev_flag_DBIN42) 
        DBIN_state[42]=1'bx;
      prev_flag_DBIN42=flag_DBIN42;
      if(flag_DBIN43!==prev_flag_DBIN43) 
        DBIN_state[43]=1'bx;
      prev_flag_DBIN43=flag_DBIN43;
      if(flag_DBIN44!==prev_flag_DBIN44) 
        DBIN_state[44]=1'bx;
      prev_flag_DBIN44=flag_DBIN44;
      if(flag_DBIN45!==prev_flag_DBIN45) 
        DBIN_state[45]=1'bx;
      prev_flag_DBIN45=flag_DBIN45;
      if(flag_DBIN46!==prev_flag_DBIN46) 
        DBIN_state[46]=1'bx;
      prev_flag_DBIN46=flag_DBIN46;
      if(flag_DBIN47!==prev_flag_DBIN47) 
        DBIN_state[47]=1'bx;
      prev_flag_DBIN47=flag_DBIN47;
      if(flag_WEB0!==prev_flag_WEB0)
        WEB_state[0]=1'bx;
      prev_flag_WEB0=flag_WEB0;
      if(flag_WEB1!==prev_flag_WEB1)
        WEB_state[1]=1'bx;
      prev_flag_WEB1=flag_WEB1;
      if(flag_WEB2!==prev_flag_WEB2)
        WEB_state[2]=1'bx;
      prev_flag_WEB2=flag_WEB2;
      if(flag_WEB3!==prev_flag_WEB3)
        WEB_state[3]=1'bx;
      prev_flag_WEB3=flag_WEB3;
      if(flag_WEB4!==prev_flag_WEB4)
        WEB_state[4]=1'bx;
      prev_flag_WEB4=flag_WEB4;
      if(flag_WEB5!==prev_flag_WEB5)
        WEB_state[5]=1'bx;
      prev_flag_WEB5=flag_WEB5;
      if(flag_WEB6!==prev_flag_WEB6)
        WEB_state[6]=1'bx;
      prev_flag_WEB6=flag_WEB6;
      if(flag_WEB7!==prev_flag_WEB7)
        WEB_state[7]=1'bx;
      prev_flag_WEB7=flag_WEB7;
      if(flag_WEB8!==prev_flag_WEB8)
        WEB_state[8]=1'bx;
      prev_flag_WEB8=flag_WEB8;
      if(flag_WEB9!==prev_flag_WEB9)
        WEB_state[9]=1'bx;
      prev_flag_WEB9=flag_WEB9;
      if(flag_WEB10!==prev_flag_WEB10)
        WEB_state[10]=1'bx;
      prev_flag_WEB10=flag_WEB10;
      if(flag_WEB11!==prev_flag_WEB11)
        WEB_state[11]=1'bx;
      prev_flag_WEB11=flag_WEB11;
      if(flag_VIOB!==prev_flag_VIOB)
        begin
	  for(wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEA_state[wn]===1'b0 && WEB_int[wn] !==1'b0)
	        for(i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
	      else if(WEB_int[wn]===1'b0 && WEA_state[wn] !== 1'b0)
	         for(i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
    	      else if(WEB_int[wn] !== 1'b0)
    		begin
		  if(^(ADB_int)===1'bx)
    		    begin
    		      for (i=0;i<Word_Depth;i=i+1)
    			begin
    			  t_data=mem_array[i];
    			  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
    			  mem_array[i]=t_data;
    			end
    		    end
    		  else
    		    begin
    		      t_data=mem_array[ADB_int];
    		      for(i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
    		      mem_array[ADB_int]=t_data;
    		    end
		end
    	    end
	  prev_flag_VIOB=flag_VIOB;
	end
      else 
        rw_memB;
    end

  task rw_memA;
    begin
      if(CLKA_state===1'bx) 
    	begin
    	  for(i=0;i<Word_Depth;i=i+1)
    	    mem_array[i]={Word_Width{1'bx}};
    	  DAOUT_state={Word_Width{1'bx}};
    	end
      else if(CENA_state===1'b0)
    	begin
	  for (wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEA_state[wn]===1'b0)	
    	        begin
    	          if(^(ADA_state)===1'bx)
   	            for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
    	          else
   	            t_data=mem_array[ADA_state];
		    for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=t_data[i];
    	        end
    	      else if(WEA_state[wn]===1'b1)
    	        begin
    	          if(^(ADA_state)===1'bx)
    		    begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
                      for(i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
    		    end		
    	          else
    		    begin
	              t_data=mem_array[ADA_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=DAIN_state[i];
		      mem_array[ADA_state]=t_data;
                      for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=t_data[i];
    		    end
    	        end
    	      else 
    	        begin
   	          for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
     	          if(^(ADA_state)===1'bx)
   	            begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
	            end		
    	          else
   	            begin
	              t_data=mem_array[ADA_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
		      mem_array[ADA_state]=t_data;
   	            end
    	        end
	    end 	
    	end		    
      else if(CENA_state===1'bx)
    	begin
	  for (wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEA_state[wn]===1'b0)
   	        for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;	      
    	      else 
    	        begin
   	          for (i=lbit;i<=hbit;i=i+1) DAOUT_state[i]=1'bx;
     	          if(^(ADA_state)===1'bx)
   	            begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
	            end		
    	          else
   	            begin
	              t_data=mem_array[ADA_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
		      mem_array[ADA_state]=t_data;
   	            end
    	        end
    	    end
        end
    end	
  endtask
  
  task rw_memB;
    begin
      if(CLKB_state===1'bx) 
    	begin
    	  for(i=0;i<Word_Depth;i=i+1)
    	    mem_array[i]={Word_Width{1'bx}};
    	  DBOUT_state={Word_Width{1'bx}};
    	end
      else if(CENB_state===1'b0)
    	begin
	  for (wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEB_state[wn]===1'b0)	
    	        begin
    	          if(^(ADB_state)===1'bx)
   	            for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
    	          else
   	            t_data=mem_array[ADB_state];
		    for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=t_data[i];
    	        end
    	      else if(WEB_state[wn]===1'b1)
    	        begin
    	          if(^(ADB_state)===1'bx)
    		    begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
                      for(i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
    		    end		
    	          else
    		    begin
	              t_data=mem_array[ADB_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=DBIN_state[i];
		      mem_array[ADB_state]=t_data;
                      for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=t_data[i];
    		    end
    	        end
    	      else 
    	        begin
   	          for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
     	          if(^(ADB_state)===1'bx)
   	            begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
	            end		
    	          else
   	            begin
	              t_data=mem_array[ADB_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
		      mem_array[ADB_state]=t_data;
   	            end
    	        end
	    end 	
    	end		    
      else if(CENB_state===1'bx)
    	begin
	  for (wn=0;wn<We_Number;wn=wn+1)
            begin
	      lbit=wn*Pt_Number;
	      if (Word_Width <= (lbit+Pt_Number)) hbit=Word_Width-1;
	      else hbit=lbit+Pt_Number-1;
	      if(WEB_state[wn]===1'b0)
   	        for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;	      
    	      else 
    	        begin
   	          for (i=lbit;i<=hbit;i=i+1) DBOUT_state[i]=1'bx;
     	          if(^(ADB_state)===1'bx)
   	            begin
   	              for (i=0;i<Word_Depth;i=i+1)
		        begin
		          t_data=mem_array[i];
   	                  for (j=lbit;j<=hbit;j=j+1) t_data[j]=1'bx;
		          mem_array[i]=t_data;
		        end
	            end		
    	          else
   	            begin
	              t_data=mem_array[ADB_state];
   	              for (i=lbit;i<=hbit;i=i+1) t_data[i]=1'bx;
		      mem_array[ADB_state]=t_data;
   	            end
    	        end
    	    end
        end
    end	
  endtask
  
  specify
    (posedge CLKA=>(DAOUT[0] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[0] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[0])=(0,0,0,0,0,0);
    (OEB=>DBOUT[0])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[1] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[1] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[1])=(0,0,0,0,0,0);
    (OEB=>DBOUT[1])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[2] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[2] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[2])=(0,0,0,0,0,0);
    (OEB=>DBOUT[2])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[3] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[3] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[3])=(0,0,0,0,0,0);
    (OEB=>DBOUT[3])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[4] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[4] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[4])=(0,0,0,0,0,0);
    (OEB=>DBOUT[4])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[5] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[5] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[5])=(0,0,0,0,0,0);
    (OEB=>DBOUT[5])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[6] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[6] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[6])=(0,0,0,0,0,0);
    (OEB=>DBOUT[6])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[7] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[7] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[7])=(0,0,0,0,0,0);
    (OEB=>DBOUT[7])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[8] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[8] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[8])=(0,0,0,0,0,0);
    (OEB=>DBOUT[8])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[9] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[9] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[9])=(0,0,0,0,0,0);
    (OEB=>DBOUT[9])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[10] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[10] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[10])=(0,0,0,0,0,0);
    (OEB=>DBOUT[10])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[11] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[11] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[11])=(0,0,0,0,0,0);
    (OEB=>DBOUT[11])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[12] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[12] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[12])=(0,0,0,0,0,0);
    (OEB=>DBOUT[12])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[13] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[13] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[13])=(0,0,0,0,0,0);
    (OEB=>DBOUT[13])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[14] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[14] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[14])=(0,0,0,0,0,0);
    (OEB=>DBOUT[14])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[15] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[15] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[15])=(0,0,0,0,0,0);
    (OEB=>DBOUT[15])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[16] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[16] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[16])=(0,0,0,0,0,0);
    (OEB=>DBOUT[16])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[17] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[17] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[17])=(0,0,0,0,0,0);
    (OEB=>DBOUT[17])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[18] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[18] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[18])=(0,0,0,0,0,0);
    (OEB=>DBOUT[18])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[19] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[19] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[19])=(0,0,0,0,0,0);
    (OEB=>DBOUT[19])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[20] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[20] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[20])=(0,0,0,0,0,0);
    (OEB=>DBOUT[20])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[21] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[21] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[21])=(0,0,0,0,0,0);
    (OEB=>DBOUT[21])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[22] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[22] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[22])=(0,0,0,0,0,0);
    (OEB=>DBOUT[22])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[23] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[23] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[23])=(0,0,0,0,0,0);
    (OEB=>DBOUT[23])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[24] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[24] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[24])=(0,0,0,0,0,0);
    (OEB=>DBOUT[24])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[25] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[25] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[25])=(0,0,0,0,0,0);
    (OEB=>DBOUT[25])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[26] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[26] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[26])=(0,0,0,0,0,0);
    (OEB=>DBOUT[26])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[27] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[27] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[27])=(0,0,0,0,0,0);
    (OEB=>DBOUT[27])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[28] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[28] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[28])=(0,0,0,0,0,0);
    (OEB=>DBOUT[28])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[29] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[29] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[29])=(0,0,0,0,0,0);
    (OEB=>DBOUT[29])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[30] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[30] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[30])=(0,0,0,0,0,0);
    (OEB=>DBOUT[30])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[31] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[31] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[31])=(0,0,0,0,0,0);
    (OEB=>DBOUT[31])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[32] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[32] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[32])=(0,0,0,0,0,0);
    (OEB=>DBOUT[32])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[33] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[33] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[33])=(0,0,0,0,0,0);
    (OEB=>DBOUT[33])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[34] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[34] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[34])=(0,0,0,0,0,0);
    (OEB=>DBOUT[34])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[35] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[35] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[35])=(0,0,0,0,0,0);
    (OEB=>DBOUT[35])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[36] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[36] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[36])=(0,0,0,0,0,0);
    (OEB=>DBOUT[36])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[37] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[37] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[37])=(0,0,0,0,0,0);
    (OEB=>DBOUT[37])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[38] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[38] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[38])=(0,0,0,0,0,0);
    (OEB=>DBOUT[38])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[39] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[39] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[39])=(0,0,0,0,0,0);
    (OEB=>DBOUT[39])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[40] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[40] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[40])=(0,0,0,0,0,0);
    (OEB=>DBOUT[40])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[41] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[41] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[41])=(0,0,0,0,0,0);
    (OEB=>DBOUT[41])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[42] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[42] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[42])=(0,0,0,0,0,0);
    (OEB=>DBOUT[42])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[43] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[43] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[43])=(0,0,0,0,0,0);
    (OEB=>DBOUT[43])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[44] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[44] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[44])=(0,0,0,0,0,0);
    (OEB=>DBOUT[44])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[45] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[45] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[45])=(0,0,0,0,0,0);
    (OEB=>DBOUT[45])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[46] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[46] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[46])=(0,0,0,0,0,0);
    (OEB=>DBOUT[46])=(0,0,0,0,0,0);
    (posedge CLKA=>(DAOUT[47] : 1'bx))=(1.000,1.000);
    (posedge CLKB=>(DBOUT[47] : 1'bx))=(1.000,1.000);
    (OEA=>DAOUT[47])=(0,0,0,0,0,0);
    (OEB=>DBOUT[47])=(0,0,0,0,0,0);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[0],0,0,flag_ADA0);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[0],0,0,flag_ADA0);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[0],0,0,flag_ADB0);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[0],0,0,flag_ADB0);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[1],0,0,flag_ADA1);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[1],0,0,flag_ADA1);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[1],0,0,flag_ADB1);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[1],0,0,flag_ADB1);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[2],0,0,flag_ADA2);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[2],0,0,flag_ADA2);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[2],0,0,flag_ADB2);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[2],0,0,flag_ADB2);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[3],0,0,flag_ADA3);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[3],0,0,flag_ADA3);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[3],0,0,flag_ADB3);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[3],0,0,flag_ADB3);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[4],0,0,flag_ADA4);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[4],0,0,flag_ADA4);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[4],0,0,flag_ADB4);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[4],0,0,flag_ADB4);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[5],0,0,flag_ADA5);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[5],0,0,flag_ADA5);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[5],0,0,flag_ADB5);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[5],0,0,flag_ADB5);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[6],0,0,flag_ADA6);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[6],0,0,flag_ADA6);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[6],0,0,flag_ADB6);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[6],0,0,flag_ADB6);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[7],0,0,flag_ADA7);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[7],0,0,flag_ADA7);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[7],0,0,flag_ADB7);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[7],0,0,flag_ADB7);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[8],0,0,flag_ADA8);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[8],0,0,flag_ADA8);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[8],0,0,flag_ADB8);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[8],0,0,flag_ADB8);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[9],0,0,flag_ADA9);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[9],0,0,flag_ADA9);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[9],0,0,flag_ADB9);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[9],0,0,flag_ADB9);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[10],0,0,flag_ADA10);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[10],0,0,flag_ADA10);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[10],0,0,flag_ADB10);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[10],0,0,flag_ADB10);
    $setuphold(posedge CLKA &&& flag_opA,posedge ADA[11],0,0,flag_ADA11);
    $setuphold(posedge CLKA &&& flag_opA,negedge ADA[11],0,0,flag_ADA11);
    $setuphold(posedge CLKB &&& flag_opB,posedge ADB[11],0,0,flag_ADB11);
    $setuphold(posedge CLKB &&& flag_opB,negedge ADB[11],0,0,flag_ADB11);
    $setuphold(posedge CLKA,posedge CENA,0,0,flag_CENA);
    $setuphold(posedge CLKA,negedge CENA,0,0,flag_CENA);
    $setuphold(posedge CLKB,posedge CENB,0,0,flag_CENB);
    $setuphold(posedge CLKB,negedge CENB,0,0,flag_CENB);
    $period(posedge CLKA,2.000,flag_CLKA_CYC);
    $period(negedge CLKA,2.000,flag_CLKA_CYC);
    $period(posedge CLKB,2.000,flag_CLKB_CYC);
    $period(negedge CLKB,2.000,flag_CLKB_CYC);
    $width(posedge CLKA,1.000,0,flag_CLKA_HT);
    $width(posedge CLKB,1.000,0,flag_CLKB_HT);
    $width(negedge CLKA,1.000,0,flag_CLKA_LT);
    $width(negedge CLKB,1.000,0,flag_CLKB_LT);
    $setup(posedge CLKA,posedge CLKB &&& flag_confB,2.000,flag_VIOB);
    $setup(posedge CLKB,posedge CLKA &&& flag_confA,2.000,flag_VIOA);
    $hold(posedge CLKA,posedge CLKB &&& flag_conf,0.010,flag_VIOB);
    $hold(posedge CLKB,posedge CLKA &&& flag_conf,0.010,flag_VIOA);
    $setuphold(posedge CLKA &&& flag_wrA0,posedge DAIN[0],0,0,flag_DAIN0);
    $setuphold(posedge CLKA &&& flag_wrA0,negedge DAIN[0],0,0,flag_DAIN0);
    $setuphold(posedge CLKB &&& flag_wrB0,posedge DBIN[0],0,0,flag_DBIN0);
    $setuphold(posedge CLKB &&& flag_wrB0,negedge DBIN[0],0,0,flag_DBIN0);
    $setuphold(posedge CLKA &&& flag_wrA0,posedge DAIN[1],0,0,flag_DAIN1);
    $setuphold(posedge CLKA &&& flag_wrA0,negedge DAIN[1],0,0,flag_DAIN1);
    $setuphold(posedge CLKB &&& flag_wrB0,posedge DBIN[1],0,0,flag_DBIN1);
    $setuphold(posedge CLKB &&& flag_wrB0,negedge DBIN[1],0,0,flag_DBIN1);
    $setuphold(posedge CLKA &&& flag_wrA0,posedge DAIN[2],0,0,flag_DAIN2);
    $setuphold(posedge CLKA &&& flag_wrA0,negedge DAIN[2],0,0,flag_DAIN2);
    $setuphold(posedge CLKB &&& flag_wrB0,posedge DBIN[2],0,0,flag_DBIN2);
    $setuphold(posedge CLKB &&& flag_wrB0,negedge DBIN[2],0,0,flag_DBIN2);
    $setuphold(posedge CLKA &&& flag_wrA0,posedge DAIN[3],0,0,flag_DAIN3);
    $setuphold(posedge CLKA &&& flag_wrA0,negedge DAIN[3],0,0,flag_DAIN3);
    $setuphold(posedge CLKB &&& flag_wrB0,posedge DBIN[3],0,0,flag_DBIN3);
    $setuphold(posedge CLKB &&& flag_wrB0,negedge DBIN[3],0,0,flag_DBIN3);
    $setuphold(posedge CLKA &&& flag_wrA1,posedge DAIN[4],0,0,flag_DAIN4);
    $setuphold(posedge CLKA &&& flag_wrA1,negedge DAIN[4],0,0,flag_DAIN4);
    $setuphold(posedge CLKB &&& flag_wrB1,posedge DBIN[4],0,0,flag_DBIN4);
    $setuphold(posedge CLKB &&& flag_wrB1,negedge DBIN[4],0,0,flag_DBIN4);
    $setuphold(posedge CLKA &&& flag_wrA1,posedge DAIN[5],0,0,flag_DAIN5);
    $setuphold(posedge CLKA &&& flag_wrA1,negedge DAIN[5],0,0,flag_DAIN5);
    $setuphold(posedge CLKB &&& flag_wrB1,posedge DBIN[5],0,0,flag_DBIN5);
    $setuphold(posedge CLKB &&& flag_wrB1,negedge DBIN[5],0,0,flag_DBIN5);
    $setuphold(posedge CLKA &&& flag_wrA1,posedge DAIN[6],0,0,flag_DAIN6);
    $setuphold(posedge CLKA &&& flag_wrA1,negedge DAIN[6],0,0,flag_DAIN6);
    $setuphold(posedge CLKB &&& flag_wrB1,posedge DBIN[6],0,0,flag_DBIN6);
    $setuphold(posedge CLKB &&& flag_wrB1,negedge DBIN[6],0,0,flag_DBIN6);
    $setuphold(posedge CLKA &&& flag_wrA1,posedge DAIN[7],0,0,flag_DAIN7);
    $setuphold(posedge CLKA &&& flag_wrA1,negedge DAIN[7],0,0,flag_DAIN7);
    $setuphold(posedge CLKB &&& flag_wrB1,posedge DBIN[7],0,0,flag_DBIN7);
    $setuphold(posedge CLKB &&& flag_wrB1,negedge DBIN[7],0,0,flag_DBIN7);
    $setuphold(posedge CLKA &&& flag_wrA2,posedge DAIN[8],0,0,flag_DAIN8);
    $setuphold(posedge CLKA &&& flag_wrA2,negedge DAIN[8],0,0,flag_DAIN8);
    $setuphold(posedge CLKB &&& flag_wrB2,posedge DBIN[8],0,0,flag_DBIN8);
    $setuphold(posedge CLKB &&& flag_wrB2,negedge DBIN[8],0,0,flag_DBIN8);
    $setuphold(posedge CLKA &&& flag_wrA2,posedge DAIN[9],0,0,flag_DAIN9);
    $setuphold(posedge CLKA &&& flag_wrA2,negedge DAIN[9],0,0,flag_DAIN9);
    $setuphold(posedge CLKB &&& flag_wrB2,posedge DBIN[9],0,0,flag_DBIN9);
    $setuphold(posedge CLKB &&& flag_wrB2,negedge DBIN[9],0,0,flag_DBIN9);
    $setuphold(posedge CLKA &&& flag_wrA2,posedge DAIN[10],0,0,flag_DAIN10);
    $setuphold(posedge CLKA &&& flag_wrA2,negedge DAIN[10],0,0,flag_DAIN10);
    $setuphold(posedge CLKB &&& flag_wrB2,posedge DBIN[10],0,0,flag_DBIN10);
    $setuphold(posedge CLKB &&& flag_wrB2,negedge DBIN[10],0,0,flag_DBIN10);
    $setuphold(posedge CLKA &&& flag_wrA2,posedge DAIN[11],0,0,flag_DAIN11);
    $setuphold(posedge CLKA &&& flag_wrA2,negedge DAIN[11],0,0,flag_DAIN11);
    $setuphold(posedge CLKB &&& flag_wrB2,posedge DBIN[11],0,0,flag_DBIN11);
    $setuphold(posedge CLKB &&& flag_wrB2,negedge DBIN[11],0,0,flag_DBIN11);
    $setuphold(posedge CLKA &&& flag_wrA3,posedge DAIN[12],0,0,flag_DAIN12);
    $setuphold(posedge CLKA &&& flag_wrA3,negedge DAIN[12],0,0,flag_DAIN12);
    $setuphold(posedge CLKB &&& flag_wrB3,posedge DBIN[12],0,0,flag_DBIN12);
    $setuphold(posedge CLKB &&& flag_wrB3,negedge DBIN[12],0,0,flag_DBIN12);
    $setuphold(posedge CLKA &&& flag_wrA3,posedge DAIN[13],0,0,flag_DAIN13);
    $setuphold(posedge CLKA &&& flag_wrA3,negedge DAIN[13],0,0,flag_DAIN13);
    $setuphold(posedge CLKB &&& flag_wrB3,posedge DBIN[13],0,0,flag_DBIN13);
    $setuphold(posedge CLKB &&& flag_wrB3,negedge DBIN[13],0,0,flag_DBIN13);
    $setuphold(posedge CLKA &&& flag_wrA3,posedge DAIN[14],0,0,flag_DAIN14);
    $setuphold(posedge CLKA &&& flag_wrA3,negedge DAIN[14],0,0,flag_DAIN14);
    $setuphold(posedge CLKB &&& flag_wrB3,posedge DBIN[14],0,0,flag_DBIN14);
    $setuphold(posedge CLKB &&& flag_wrB3,negedge DBIN[14],0,0,flag_DBIN14);
    $setuphold(posedge CLKA &&& flag_wrA3,posedge DAIN[15],0,0,flag_DAIN15);
    $setuphold(posedge CLKA &&& flag_wrA3,negedge DAIN[15],0,0,flag_DAIN15);
    $setuphold(posedge CLKB &&& flag_wrB3,posedge DBIN[15],0,0,flag_DBIN15);
    $setuphold(posedge CLKB &&& flag_wrB3,negedge DBIN[15],0,0,flag_DBIN15);
    $setuphold(posedge CLKA &&& flag_wrA4,posedge DAIN[16],0,0,flag_DAIN16);
    $setuphold(posedge CLKA &&& flag_wrA4,negedge DAIN[16],0,0,flag_DAIN16);
    $setuphold(posedge CLKB &&& flag_wrB4,posedge DBIN[16],0,0,flag_DBIN16);
    $setuphold(posedge CLKB &&& flag_wrB4,negedge DBIN[16],0,0,flag_DBIN16);
    $setuphold(posedge CLKA &&& flag_wrA4,posedge DAIN[17],0,0,flag_DAIN17);
    $setuphold(posedge CLKA &&& flag_wrA4,negedge DAIN[17],0,0,flag_DAIN17);
    $setuphold(posedge CLKB &&& flag_wrB4,posedge DBIN[17],0,0,flag_DBIN17);
    $setuphold(posedge CLKB &&& flag_wrB4,negedge DBIN[17],0,0,flag_DBIN17);
    $setuphold(posedge CLKA &&& flag_wrA4,posedge DAIN[18],0,0,flag_DAIN18);
    $setuphold(posedge CLKA &&& flag_wrA4,negedge DAIN[18],0,0,flag_DAIN18);
    $setuphold(posedge CLKB &&& flag_wrB4,posedge DBIN[18],0,0,flag_DBIN18);
    $setuphold(posedge CLKB &&& flag_wrB4,negedge DBIN[18],0,0,flag_DBIN18);
    $setuphold(posedge CLKA &&& flag_wrA4,posedge DAIN[19],0,0,flag_DAIN19);
    $setuphold(posedge CLKA &&& flag_wrA4,negedge DAIN[19],0,0,flag_DAIN19);
    $setuphold(posedge CLKB &&& flag_wrB4,posedge DBIN[19],0,0,flag_DBIN19);
    $setuphold(posedge CLKB &&& flag_wrB4,negedge DBIN[19],0,0,flag_DBIN19);
    $setuphold(posedge CLKA &&& flag_wrA5,posedge DAIN[20],0,0,flag_DAIN20);
    $setuphold(posedge CLKA &&& flag_wrA5,negedge DAIN[20],0,0,flag_DAIN20);
    $setuphold(posedge CLKB &&& flag_wrB5,posedge DBIN[20],0,0,flag_DBIN20);
    $setuphold(posedge CLKB &&& flag_wrB5,negedge DBIN[20],0,0,flag_DBIN20);
    $setuphold(posedge CLKA &&& flag_wrA5,posedge DAIN[21],0,0,flag_DAIN21);
    $setuphold(posedge CLKA &&& flag_wrA5,negedge DAIN[21],0,0,flag_DAIN21);
    $setuphold(posedge CLKB &&& flag_wrB5,posedge DBIN[21],0,0,flag_DBIN21);
    $setuphold(posedge CLKB &&& flag_wrB5,negedge DBIN[21],0,0,flag_DBIN21);
    $setuphold(posedge CLKA &&& flag_wrA5,posedge DAIN[22],0,0,flag_DAIN22);
    $setuphold(posedge CLKA &&& flag_wrA5,negedge DAIN[22],0,0,flag_DAIN22);
    $setuphold(posedge CLKB &&& flag_wrB5,posedge DBIN[22],0,0,flag_DBIN22);
    $setuphold(posedge CLKB &&& flag_wrB5,negedge DBIN[22],0,0,flag_DBIN22);
    $setuphold(posedge CLKA &&& flag_wrA5,posedge DAIN[23],0,0,flag_DAIN23);
    $setuphold(posedge CLKA &&& flag_wrA5,negedge DAIN[23],0,0,flag_DAIN23);
    $setuphold(posedge CLKB &&& flag_wrB5,posedge DBIN[23],0,0,flag_DBIN23);
    $setuphold(posedge CLKB &&& flag_wrB5,negedge DBIN[23],0,0,flag_DBIN23);
    $setuphold(posedge CLKA &&& flag_wrA6,posedge DAIN[24],0,0,flag_DAIN24);
    $setuphold(posedge CLKA &&& flag_wrA6,negedge DAIN[24],0,0,flag_DAIN24);
    $setuphold(posedge CLKB &&& flag_wrB6,posedge DBIN[24],0,0,flag_DBIN24);
    $setuphold(posedge CLKB &&& flag_wrB6,negedge DBIN[24],0,0,flag_DBIN24);
    $setuphold(posedge CLKA &&& flag_wrA6,posedge DAIN[25],0,0,flag_DAIN25);
    $setuphold(posedge CLKA &&& flag_wrA6,negedge DAIN[25],0,0,flag_DAIN25);
    $setuphold(posedge CLKB &&& flag_wrB6,posedge DBIN[25],0,0,flag_DBIN25);
    $setuphold(posedge CLKB &&& flag_wrB6,negedge DBIN[25],0,0,flag_DBIN25);
    $setuphold(posedge CLKA &&& flag_wrA6,posedge DAIN[26],0,0,flag_DAIN26);
    $setuphold(posedge CLKA &&& flag_wrA6,negedge DAIN[26],0,0,flag_DAIN26);
    $setuphold(posedge CLKB &&& flag_wrB6,posedge DBIN[26],0,0,flag_DBIN26);
    $setuphold(posedge CLKB &&& flag_wrB6,negedge DBIN[26],0,0,flag_DBIN26);
    $setuphold(posedge CLKA &&& flag_wrA6,posedge DAIN[27],0,0,flag_DAIN27);
    $setuphold(posedge CLKA &&& flag_wrA6,negedge DAIN[27],0,0,flag_DAIN27);
    $setuphold(posedge CLKB &&& flag_wrB6,posedge DBIN[27],0,0,flag_DBIN27);
    $setuphold(posedge CLKB &&& flag_wrB6,negedge DBIN[27],0,0,flag_DBIN27);
    $setuphold(posedge CLKA &&& flag_wrA7,posedge DAIN[28],0,0,flag_DAIN28);
    $setuphold(posedge CLKA &&& flag_wrA7,negedge DAIN[28],0,0,flag_DAIN28);
    $setuphold(posedge CLKB &&& flag_wrB7,posedge DBIN[28],0,0,flag_DBIN28);
    $setuphold(posedge CLKB &&& flag_wrB7,negedge DBIN[28],0,0,flag_DBIN28);
    $setuphold(posedge CLKA &&& flag_wrA7,posedge DAIN[29],0,0,flag_DAIN29);
    $setuphold(posedge CLKA &&& flag_wrA7,negedge DAIN[29],0,0,flag_DAIN29);
    $setuphold(posedge CLKB &&& flag_wrB7,posedge DBIN[29],0,0,flag_DBIN29);
    $setuphold(posedge CLKB &&& flag_wrB7,negedge DBIN[29],0,0,flag_DBIN29);
    $setuphold(posedge CLKA &&& flag_wrA7,posedge DAIN[30],0,0,flag_DAIN30);
    $setuphold(posedge CLKA &&& flag_wrA7,negedge DAIN[30],0,0,flag_DAIN30);
    $setuphold(posedge CLKB &&& flag_wrB7,posedge DBIN[30],0,0,flag_DBIN30);
    $setuphold(posedge CLKB &&& flag_wrB7,negedge DBIN[30],0,0,flag_DBIN30);
    $setuphold(posedge CLKA &&& flag_wrA7,posedge DAIN[31],0,0,flag_DAIN31);
    $setuphold(posedge CLKA &&& flag_wrA7,negedge DAIN[31],0,0,flag_DAIN31);
    $setuphold(posedge CLKB &&& flag_wrB7,posedge DBIN[31],0,0,flag_DBIN31);
    $setuphold(posedge CLKB &&& flag_wrB7,negedge DBIN[31],0,0,flag_DBIN31);
    $setuphold(posedge CLKA &&& flag_wrA8,posedge DAIN[32],0,0,flag_DAIN32);
    $setuphold(posedge CLKA &&& flag_wrA8,negedge DAIN[32],0,0,flag_DAIN32);
    $setuphold(posedge CLKB &&& flag_wrB8,posedge DBIN[32],0,0,flag_DBIN32);
    $setuphold(posedge CLKB &&& flag_wrB8,negedge DBIN[32],0,0,flag_DBIN32);
    $setuphold(posedge CLKA &&& flag_wrA8,posedge DAIN[33],0,0,flag_DAIN33);
    $setuphold(posedge CLKA &&& flag_wrA8,negedge DAIN[33],0,0,flag_DAIN33);
    $setuphold(posedge CLKB &&& flag_wrB8,posedge DBIN[33],0,0,flag_DBIN33);
    $setuphold(posedge CLKB &&& flag_wrB8,negedge DBIN[33],0,0,flag_DBIN33);
    $setuphold(posedge CLKA &&& flag_wrA8,posedge DAIN[34],0,0,flag_DAIN34);
    $setuphold(posedge CLKA &&& flag_wrA8,negedge DAIN[34],0,0,flag_DAIN34);
    $setuphold(posedge CLKB &&& flag_wrB8,posedge DBIN[34],0,0,flag_DBIN34);
    $setuphold(posedge CLKB &&& flag_wrB8,negedge DBIN[34],0,0,flag_DBIN34);
    $setuphold(posedge CLKA &&& flag_wrA8,posedge DAIN[35],0,0,flag_DAIN35);
    $setuphold(posedge CLKA &&& flag_wrA8,negedge DAIN[35],0,0,flag_DAIN35);
    $setuphold(posedge CLKB &&& flag_wrB8,posedge DBIN[35],0,0,flag_DBIN35);
    $setuphold(posedge CLKB &&& flag_wrB8,negedge DBIN[35],0,0,flag_DBIN35);
    $setuphold(posedge CLKA &&& flag_wrA9,posedge DAIN[36],0,0,flag_DAIN36);
    $setuphold(posedge CLKA &&& flag_wrA9,negedge DAIN[36],0,0,flag_DAIN36);
    $setuphold(posedge CLKB &&& flag_wrB9,posedge DBIN[36],0,0,flag_DBIN36);
    $setuphold(posedge CLKB &&& flag_wrB9,negedge DBIN[36],0,0,flag_DBIN36);
    $setuphold(posedge CLKA &&& flag_wrA9,posedge DAIN[37],0,0,flag_DAIN37);
    $setuphold(posedge CLKA &&& flag_wrA9,negedge DAIN[37],0,0,flag_DAIN37);
    $setuphold(posedge CLKB &&& flag_wrB9,posedge DBIN[37],0,0,flag_DBIN37);
    $setuphold(posedge CLKB &&& flag_wrB9,negedge DBIN[37],0,0,flag_DBIN37);
    $setuphold(posedge CLKA &&& flag_wrA9,posedge DAIN[38],0,0,flag_DAIN38);
    $setuphold(posedge CLKA &&& flag_wrA9,negedge DAIN[38],0,0,flag_DAIN38);
    $setuphold(posedge CLKB &&& flag_wrB9,posedge DBIN[38],0,0,flag_DBIN38);
    $setuphold(posedge CLKB &&& flag_wrB9,negedge DBIN[38],0,0,flag_DBIN38);
    $setuphold(posedge CLKA &&& flag_wrA9,posedge DAIN[39],0,0,flag_DAIN39);
    $setuphold(posedge CLKA &&& flag_wrA9,negedge DAIN[39],0,0,flag_DAIN39);
    $setuphold(posedge CLKB &&& flag_wrB9,posedge DBIN[39],0,0,flag_DBIN39);
    $setuphold(posedge CLKB &&& flag_wrB9,negedge DBIN[39],0,0,flag_DBIN39);
    $setuphold(posedge CLKA &&& flag_wrA10,posedge DAIN[40],0,0,flag_DAIN40);
    $setuphold(posedge CLKA &&& flag_wrA10,negedge DAIN[40],0,0,flag_DAIN40);
    $setuphold(posedge CLKB &&& flag_wrB10,posedge DBIN[40],0,0,flag_DBIN40);
    $setuphold(posedge CLKB &&& flag_wrB10,negedge DBIN[40],0,0,flag_DBIN40);
    $setuphold(posedge CLKA &&& flag_wrA10,posedge DAIN[41],0,0,flag_DAIN41);
    $setuphold(posedge CLKA &&& flag_wrA10,negedge DAIN[41],0,0,flag_DAIN41);
    $setuphold(posedge CLKB &&& flag_wrB10,posedge DBIN[41],0,0,flag_DBIN41);
    $setuphold(posedge CLKB &&& flag_wrB10,negedge DBIN[41],0,0,flag_DBIN41);
    $setuphold(posedge CLKA &&& flag_wrA10,posedge DAIN[42],0,0,flag_DAIN42);
    $setuphold(posedge CLKA &&& flag_wrA10,negedge DAIN[42],0,0,flag_DAIN42);
    $setuphold(posedge CLKB &&& flag_wrB10,posedge DBIN[42],0,0,flag_DBIN42);
    $setuphold(posedge CLKB &&& flag_wrB10,negedge DBIN[42],0,0,flag_DBIN42);
    $setuphold(posedge CLKA &&& flag_wrA10,posedge DAIN[43],0,0,flag_DAIN43);
    $setuphold(posedge CLKA &&& flag_wrA10,negedge DAIN[43],0,0,flag_DAIN43);
    $setuphold(posedge CLKB &&& flag_wrB10,posedge DBIN[43],0,0,flag_DBIN43);
    $setuphold(posedge CLKB &&& flag_wrB10,negedge DBIN[43],0,0,flag_DBIN43);
    $setuphold(posedge CLKA &&& flag_wrA11,posedge DAIN[44],0,0,flag_DAIN44);
    $setuphold(posedge CLKA &&& flag_wrA11,negedge DAIN[44],0,0,flag_DAIN44);
    $setuphold(posedge CLKB &&& flag_wrB11,posedge DBIN[44],0,0,flag_DBIN44);
    $setuphold(posedge CLKB &&& flag_wrB11,negedge DBIN[44],0,0,flag_DBIN44);
    $setuphold(posedge CLKA &&& flag_wrA11,posedge DAIN[45],0,0,flag_DAIN45);
    $setuphold(posedge CLKA &&& flag_wrA11,negedge DAIN[45],0,0,flag_DAIN45);
    $setuphold(posedge CLKB &&& flag_wrB11,posedge DBIN[45],0,0,flag_DBIN45);
    $setuphold(posedge CLKB &&& flag_wrB11,negedge DBIN[45],0,0,flag_DBIN45);
    $setuphold(posedge CLKA &&& flag_wrA11,posedge DAIN[46],0,0,flag_DAIN46);
    $setuphold(posedge CLKA &&& flag_wrA11,negedge DAIN[46],0,0,flag_DAIN46);
    $setuphold(posedge CLKB &&& flag_wrB11,posedge DBIN[46],0,0,flag_DBIN46);
    $setuphold(posedge CLKB &&& flag_wrB11,negedge DBIN[46],0,0,flag_DBIN46);
    $setuphold(posedge CLKA &&& flag_wrA11,posedge DAIN[47],0,0,flag_DAIN47);
    $setuphold(posedge CLKA &&& flag_wrA11,negedge DAIN[47],0,0,flag_DAIN47);
    $setuphold(posedge CLKB &&& flag_wrB11,posedge DBIN[47],0,0,flag_DBIN47);
    $setuphold(posedge CLKB &&& flag_wrB11,negedge DBIN[47],0,0,flag_DBIN47);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[0],0,0,flag_WEA0);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[0],0,0,flag_WEA0);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[0],0,0,flag_WEB0);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[0],0,0,flag_WEB0);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[1],0,0,flag_WEA1);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[1],0,0,flag_WEA1);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[1],0,0,flag_WEB1);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[1],0,0,flag_WEB1);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[2],0,0,flag_WEA2);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[2],0,0,flag_WEA2);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[2],0,0,flag_WEB2);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[2],0,0,flag_WEB2);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[3],0,0,flag_WEA3);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[3],0,0,flag_WEA3);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[3],0,0,flag_WEB3);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[3],0,0,flag_WEB3);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[4],0,0,flag_WEA4);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[4],0,0,flag_WEA4);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[4],0,0,flag_WEB4);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[4],0,0,flag_WEB4);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[5],0,0,flag_WEA5);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[5],0,0,flag_WEA5);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[5],0,0,flag_WEB5);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[5],0,0,flag_WEB5);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[6],0,0,flag_WEA6);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[6],0,0,flag_WEA6);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[6],0,0,flag_WEB6);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[6],0,0,flag_WEB6);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[7],0,0,flag_WEA7);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[7],0,0,flag_WEA7);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[7],0,0,flag_WEB7);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[7],0,0,flag_WEB7);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[8],0,0,flag_WEA8);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[8],0,0,flag_WEA8);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[8],0,0,flag_WEB8);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[8],0,0,flag_WEB8);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[9],0,0,flag_WEA9);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[9],0,0,flag_WEA9);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[9],0,0,flag_WEB9);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[9],0,0,flag_WEB9);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[10],0,0,flag_WEA10);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[10],0,0,flag_WEA10);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[10],0,0,flag_WEB10);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[10],0,0,flag_WEB10);
    $setuphold(posedge CLKA &&& flag_opA,posedge WEA[11],0,0,flag_WEA11);
    $setuphold(posedge CLKA &&& flag_opA,negedge WEA[11],0,0,flag_WEA11);
    $setuphold(posedge CLKB &&& flag_opB,posedge WEB[11],0,0,flag_WEB11);
    $setuphold(posedge CLKB &&& flag_opB,negedge WEB[11],0,0,flag_WEB11);
  endspecify
  
endmodule

`endcelldefine
